In a semiconductor integrated circuit device having a plurality of external terminals, when a short circuit occurs between adjacent external terminals due to various factors (e.g., adhesion of dirt and dust), the external terminals generally fail to function properly. In particular, in a high withstand voltage IC such as a motor driver IC, when an external terminal short-circuited to a high withstand voltage terminal (such as a power supply terminal) happens to have a low withstand voltage (e.g., when the external terminal serves as a logic-signal input/output terminal), an excessive current may flow through an internal component connected to the external terminal to cause breakdown or heating of the semiconductor integrated circuit device.
Conventionally, one solution to the above-described shirt circuit between terminals is to use a non-connected terminal as an external terminal adjacent to a high withstand terminal.
As another conventional technology related to the present invention, there is disclosed and proposed a so-called SiP (system in package) IC in which a plurality of circuit components constituting a plurality of circuits are optimally divided according to the levels of current, power dissipation, voltage, required withstand voltage and other factors, and, for each of the levels, the circuit components are integrated into individual semiconductor chips (for example, see patent document 1).
Patent document 1: JP-A-2004-265931